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If someone is looking for how to design AXI Lite system, then here's the axi lite master specification. I wrote the AXI Lite master part in verilog. I have used AXI Stream
Timing Diagrams for AXI lite Slave connected IP component
HOW TO CREATE an AXI4-FULL CUSTOM IP with AXI4-LITE and UART INTERFACES in VIVADO – Mehmet Burak Aykenar
Digital Protocols | John-Gentile.com
What is AXI Lite? - YouTube
Verification IP AXI4-LITE Verification IP
Figure 7 from A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC | Semantic Scholar
AMBA AXI4-Lite Verification IP
3. AXI4-Lite Cross-bar Interconnect — Interconnect IPs 1.1.6 documentation
Buidilng an AXI-Lite slave the easy way
Welcome to Real Digital
AXI-Full and AXI-Lite Interfaces - Logic Fruit Technologies
Deploy Model with AXI-Stream Interface in Zynq Workflow - MATLAB & Simulink - MathWorks France
How to send data from AXI-LITE port to PL and receive data from AXI DMA - Support - PYNQ
AMBA AXI4-Lite Interconnect Verification IP
Understanding the AMBA AXI4 Spec - Circuit Cellar
Buidilng an AXI-Lite slave the easy way
Building a custom yet functional AXI-lite slave
AXI Basics 6 - Introduction to AXI4-Lite in Vitis HLS
AXI4-Lite Interface - 4.3 English
